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LT3743
APPLICATIONS INFORMATION
? V IN ? ( V F + R D I O ) – ( V F + R D I O ) ?
2 ? f S ? L ? V IN
I MAX = I O +
? ( ( Q GD + Q GS ) ? ( 2 ? R G + R PU + R PD ) ) ? f S
SwitchingMOSFETSelection
When selecting switching MOSFETs, the following pa-
rameters are critical in determining the best devices for
a given application: total gate charge (Q G ), on-resistance
(R DS(ON) ), gate to drain charge (Q GD ), gate-to-source
charge (Q GS ), gate resistance (R G ), breakdown voltages
(maximum V GS and V DS ) and drain current (maximum I D ).
The following guidelines provide information to make the
selection process easier.
Both of the switching MOSFETs need to have their maximum
rated drain currents greater than the maximum inductor
current. The following equation calculates the peak induc-
tor current:
? 2 ?
? ?
? ?
where V IN is the input voltage, L is the inductance value, V F
is the LED forward voltage drop, R D is the dynamic series
resistance of the LED, I O is the regulated output current
and f S is the switching frequency. During MOSFET selec-
tion, notice that the maximum drain current is temperature
dependant. Most data sheets include a table or graph of
the maximum rated drain current vs temperature.
The maximum V DS should be selected to be higher than
the maximum input supply voltage (including transient)
for both MOSFETs. The signals driving the gates of the
switching MOSFETs have a maximum voltage of 5V with
respect to the source. During start-up and recovery con-
ditions, the gate drive signals may be as low as 3V. To
ensure that the LT3743 recovers properly, the maximum
threshold should be less than 2V. For a robust design,
select the maximum V GS greater than 7V.
Power losses in the switching MOSFETs are related to
the on-resistance, R DS(ON) ; the transitional loss related
to the gate resistance, R G ; gate-to-drain capacitance, Q GD
and gate-to-source capacitance, Q GS . Power loss to the
on-resistance is an Ohmic loss, I 2 R DS(ON) , and usually
dominates for input voltages less than ~15V. Power losses
to the gate capacitance dominate for voltages greater than
~12V. When operating at higher input voltages, efficiency
can be optimized by selecting a high side MOSFET with
higher R DS(ON) and lower C GD . The power loss in the high
side MOSFET can be approximated by:
P LOSS = (ohmic loss) + (transition loss)
2
P LOSS ( V F + R D I O ) ? I O R DS(ON) ? T +
V IN
V IN ? I OUT
5V
where ρ T is a temperature-dependant term of the MOS-
FET’s on-resistance. Using 70°C as the maximum ambient
operating temperature, ρ T is roughly equal to 1.3. R PD and
R PU are the LT3743 high side gate driver output imped-
ance, 1.3? and 2.3? respectively.
A good approach to MOSFET sizing is to select a high side
MOSFET, then select the low side MOSFET. The trade-
off between R DS(ON) , Q G , Q GD and Q GS for the high side
MOSFET is shown in the following example. V O is equal
to 4V. Comparing two N-channel MOSFETs, with a rated
V DS of 40V and in the same package, but with 8 × different
R DS(ON) and 4.5 × different Q G and Q GD :
M1: R DS(ON) = 2.3m?, Q G = 45.5nC,
Q GS = 13.8nC, Q GD = 14.4nC , R G = 1Ω
M2: R DS(ON) = 18m?, Q G = 10nC,
Q GS = 4.5nC, Q GD = 3.1nC , R G = 3.5Ω
Power loss for both MOSFETs is shown in Figure 4. Ob-
serve that while the R DS(ON) of M1 is eight times lower, the
power loss at low input voltages is equal, but four times
higher at high input voltages than the power loss for M2.
Another power loss related to switching MOSFET selection
is the power lost to driving the gates. The total gate charge,
Q G , must be charged and discharged each switching cycle.
The power is lost to the internal LDO within the LT3743.
The power lost to the charging of the gates is:
P LOSS_LDO ≈ (V IN – 5V ) ? ( Q GLG + Q GHG ) ? f S
where Q GLG is the low side gate charge and Q GHG is the
high side gate charge.
3743fd
14
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